1. Field
Example embodiments may relate to a voltage controlled oscillator (VCO), and more particularly, to a VCO for generating quadrature-phase clock signals.
2. Description of Related Art
A voltage controlled oscillator (VCO) is a circuit that may output a signal having a frequency that may be proportional or disproportional to a voltage applied from the outside. The VCO may be used in analog circuits or digital circuits, and particularly, in a phase locked loop (PLL) circuit, which may be employed in a radio data communication.
Examples of the VCO may include a ring oscillator and a LC oscillator, which may be selectively used according to their circuit characteristics. Recently, a complementary metal oxide semiconductor (CMOS) ring oscillator, which may be a highly integrated and low-cost circuit, has been widely used.
The CMOS ring oscillator may include an odd number of delay cells, and may have a ring structure in which a signal output from a delay cell of a last stage may be fed back to a delay cell of a first stage.
The total number of the delay cells of the ring oscillator may be inversely proportional to an output oscillation frequency. Thus, a 3-stage ring oscillator with three delay cells may be used in order to establish a high-speed data communication.
Two signals from among signals output from the 3-stage ring oscillator may be respectively phase-shifted by 120 degrees and 240 degrees with respect to the other signal.
However, quadrature-phase (4-phase) clock signals may be needed in order to reproduce data received or transmitted during a high-speed data communication. The 4-phase clock signals may also be needed in order to serialize or parallelize a data signal received or transmitted in a data pipeline stage of a semiconductor memory device, such as a dynamic random access memory (DRAM).
Thus, the ring oscillator with three delay cells may be suitable for transmission of data at high speeds but may not be suitable for a data communication requiring the 4-phase signals.
Either a ring oscillator with four delay cells or an additional circuit may be needed in order to generate the 4-phase clock signals that are phase shifted by 90 degrees with respect to one another.
FIG. 1 is a circuit diagram of a conventional PLL circuit 10 for generating 4-phase frequencies. Referring to FIG. 1, the PLL circuit 10 may have a phase/frequency detector 11, a charge pump 12, a loop filter 13, a VCO 14, a duty correction circuit 15, and a frequency divider 16. In the PLL circuit 10, in order to generate 4-phase clock signals I, IB, Q, and QB having a desired frequency, e.g., 2.5 GHz, the VCO 14 may generate a clock signal having a frequency, e.g., 5.0 GHz, which may be twice the value of a desired frequency. The clock signal may pass through the frequency divider 16, which may be embodied as a flip-flop, thus generating the 4-phase clock signals I, IB, Q, and QB having the desired frequency.
Therefore, in order to generate the 4-phase clock signals, an additional frequency divider may be needed, which may complicate the construction of a circuit.